Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored information when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and phase change random access memory (PCRAM), among others.
Various types of memory can be used in memory systems. For example, Flash memory can be part of a memory system as internal memory or as removable memory that can be coupled to the memory system through an interface via a format such as USB (universal serial bus), MMC (multi media card), CF (compact flash), or SD (secure digital), among others. Flash memory devices, including floating gate flash devices and charge trap flash (CTF) devices, may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for sold state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among others. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line (e.g., a word line as commonly referred to in the art). However each memory cell is not directly coupled to a data line (e.g., a bit line as commonly referred to in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a bit line, where the memory cells commonly coupled to a particular bit line are referred to as a “column”.
NAND memory devices can include a number of arrays of memory cells organized into physical blocks of memory cells. When accessing memory cells within a block of memory cells, different sets of word lines within the block can be biased with different voltages depending upon the desired operation and the relation of the set of word lines to a target (e.g., a selected) word line. During access operations (e.g., program operations, verify operations, or read operations), other portions of a memory cell (e.g., a well, a source region, or bit line) can also be biased with different voltages depending upon the desired operation and the relation of the set of word lines to the target word line.
For instance, several different program inhibit schemes (e.g., techniques) can be used in association with a program operation, depending upon the position of a target word line. Examples of different program inhibit techniques include self-boosting, erased area self-boosting (EASB), revised erased area self-boosting (REASB), local self-boosting (LSB), and revised local self-boosting (RLSB).
Using different biasing schemes depending on the position of a target word line can provide various benefits. For instance, using different program inhibit schemes can reduce program disturb and/or read disturb, among other benefits.